1. Technical Field
This disclosure relates to semiconductor testing and more particularly, to a method for measuring electrical characteristics of a single active device on a semiconductor chip.
2. Description of the Related Art
Semiconductor devices are fabricated and tested by employing pattern generators and testers. Also, visual inspections of wafers are employed to determine defects or other abnormalities on the wafers. In some instances, testing is extended to determine failure modes which are experienced in a lot of wafers or on an individual chip. These failure modes determine why or how a failure has occurred. In such instances, it is desirable to focus in detail on the mechanisms which caused failures or on the components which have failed.
In semiconductor memory devices, the characteristics of transfer gates (transistors) in an electrical circuit are among the main parameters, which define the function and performance of semiconductor devices. Usually the design of electrical circuits does not permit an individual probing of a source and drain of a transistor without prior modification of the device. This is especially true in the case of a dense array of memory cells in deep trench (DT) technology. Important information about the characteristics of these cells is mainly based on the performance of specially designed kerf (test) structures (e.g. embedded nominal device). These test structures do not provide information about particular devices themselves, however. It would be beneficial to be able to test a single memory cell in an array of cells for a better understanding of leakage mechanisms and cell performance in an actual device.
Therefore, a need exists for a method for testing individual devices on a semiconductor device.